The AI industry talks constantly about models and GPUs. Far less attention goes to the precision tools that make advanced chips possible. ASML’s latest plan shows that a change deep inside the factory can shape the economics of tomorrow’s data centres.
Reuters reported on 8 September 2026 that Dutch chip-equipment maker ASML will work with Nvidia, Intel, TSMC and Samsung on larger masks for its newest High Numerical Aperture extreme-ultraviolet lithography systems. SK Hynix has also expressed interest in the effort.
ASML says a pilot is planned for 2031 and the larger-mask approach is intended to be ready for high-volume manufacturing in 2033. Those are roadmap dates, not evidence of commercial deployment today. The distinction matters because semiconductor development can change over many years of testing.
What a photomask does
A modern chip contains billions of microscopic features arranged in precise layers. Lithography projects a pattern from a mask—often called a reticle—onto a light-sensitive wafer. This happens repeatedly as the chip’s electrical structures are built.
High-NA EUV can print finer features than earlier EUV systems, but its optical field creates limits on the area that can be exposed at once. That matters for large AI accelerators and data-centre processors, which push against the maximum practical size of an individual die or package component.
A more powerful chip does not begin with code. It begins with the physical ability to print reliable patterns at extraordinary precision.
Why larger masks matter
Reuters reported that current EUV tools can support chips up to roughly 800 square millimetres, while the present High-NA format constrains larger designs. ASML’s proposed larger masks aim to recover more usable chip area while preserving High-NA’s finer printing capability.
The company also estimates the format could improve system productivity by about 40 percent. That figure is a company projection and will have to be demonstrated in manufacturing conditions. If achieved, it could spread the enormous cost of the equipment across more useful output.
The AI-chip design pressure
AI workloads reward dense computing, fast memory connections and high-bandwidth communication. Designers have several ways to meet that demand. They can build a larger monolithic die, combine smaller chiplets inside one package or distribute work across multiple accelerators.
Larger masks do not eliminate the yield problem: the bigger a single die becomes, the greater the chance that a manufacturing defect affects it. Nor do they replace advanced packaging. Instead, they expand the design choices available to chipmakers and may make some large components more practical.
- Larger compute dies where a workload benefits from tightly integrated circuitry.
- More efficient exposure of large designs during manufacturing.
- New packaging combinations involving compute, memory and interconnect components.
- Potential productivity gains that partially offset the extreme cost of High-NA tools.
- A longer runway for data-centre chips before physical field limits become restrictive.
The consortium reveals the real AI stack
The participants span different parts of the semiconductor economy: equipment, foundries, memory, chip design and integrated manufacturing. Their cooperation illustrates a crucial point. No company controls the entire chain required to turn frontier AI demand into physical processors.
That interdependence is why semiconductor capacity has become foreign policy, as explored in Taiwan’s chip diplomacy. It also explains strategic investments such as Nvidia’s MediaTek deal and the consumer consequences examined in RAMageddon.
Why the 2030s roadmap matters today
A 2033 manufacturing target may sound distant, but fabs and chip architectures are planned years in advance. Companies deciding on future data-centre designs need to know which manufacturing options may be available. Governments deciding where to subsidise factories need to understand which equipment ecosystems those factories will depend upon.
The broader lesson is that AI capability is constrained not only by algorithms, but by a long chain of materials, optics, machines, power and specialised knowledge. Software can advance quickly; the physical stack requires long-term coordination.
Explore the MaryChuks Digital Store for more practical technology and AI-business resources.
Discussion question: Will the next generation of AI computing be driven more by larger individual chips, or by smarter systems that combine many smaller chiplets?
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